The conventional approach to electronic packaging and interconnect has been to package individual integrated circuit (IC) chips into a single package and to attach these packages to a printed circuit board to provide interconnect between the individual IC chips. In recent years, this approach has met with problems of speed, size and interconnect density due to ever-constant demands for reduced size and increased performance from such integrated circuit packages.
Process speed is conventionally limited by the fact that individual packages have loading capacitance and inductance associated with their relatively long pins and by the large size of conductor runs in the packages relative to the size of the conductors of a bare IC chip. As the speed of computers and other devices continues to increase, the problem of providing electronic packaging and interconnect which provides maximum performance has become a significant challenge. One solution to the problem is the multichip module (MCM). In an MCM, bare (unpackaged) IC chips are interconnected by means of a miniature printed circuit board whose interconnect pitch may match the pitch of the IC chips themselves. There are presently two main classes of MCM. These are the chips-last MCM and the chips-first MCM. In the chips-last MCM, the miniature circuit board is fabricated first and then the bare IC chips are attached and interconnected to the circuit board. The method of interconnect is usually wire-bond or solder bump. In the chips-first MCM, the chips are placed first relative to each other and a miniature circuit board is then built above the chips.
Structures in accordance with the present invention fall into the category of chips-first MCMs. Chips-first MCMs provide one way to minimize size of a multichip module and provide high performance interconnect. Examples of chips-first modules are given in U.S. Pat. Nos. 5,250,843; 5,353,498; and 5,841,193, each of which is hereby incorporated herein by reference in its entirety.
In a chips-first circuit structure, the front surface of the chip layer is conventionally covered by a dielectric layer, which is patterned with via holes exposing contact pads on the upper surfaces of the chips of the chip layer. A metallization is then applied and patterned to make electrical contact to the contact pads and form the interconnect. As a further step, a solder mask may be provided above the dielectric layer with openings to expose the metallization layer, and solder bumps added to provide an electrical interconnect means for connecting the electronic module to, for example, a printed circuit board. In all cases, the dielectric layer is utilized over the chips-first circuit structure, with multiple via openings to the chips' contact pads.
One problem with this approach is that a tight pad pitch can be difficult to connect to when employing a dielectric layer with multiple via openings to interconnect the chips of the chips-first layer. This is because the dielectric layer is relatively thick, and the resolution ability of the dielectric may prevent making the desired via hole pitch. Also, any resist that is used to pattern the metallization layer must also fill the via hole. This increases the effective thickness of the resist, and makes patterning the metal layer more difficult than if the whole assembly was essentially planar.
Another problem with the above-described chips-first interconnect approach is that lithography steps in the process are among the most expensive to perform, and have the greatest impact on process yield. In high volume packaging, fewer lithography steps translates directly into lower cost. In the existing approach, the first interconnect layer is formed by patterning individual via holes in the dielectric layer, and then patterning the metallization. Each of these patterning steps requires at least one lithography step.